As the semiconductor industry has continued to progress toward microdevices, complementary metal-oxide-semiconductor (CMOS) circuits have become increasingly more highly integrated. Consequently, the individual devices which are combined to form CMOS circuits have become increasingly smaller. In some instances, the scaling down of these devices has created a need for new technologies, as existing technologies have run into fundamental limitations that prevent the devices from being scaled down any further.
For example, in conventional metal-oxide-silicon field effect transistor (“MOSFET”) devices in which a gate controls a channel and the channel provides a path between a source region and a drain region, the smaller dimensions of the channel may cause the source and drain regions to be too close to one another. As a result of the shortened distance, leakage current may flow between the source and drain regions. Additionally, the ability to control the gate may be decreased.
To address the above issues, double gate field effect transistors, typically fin-type field effect transistors (“finFET”) have been used. FinFETs are capable of relatively high transconductance and improved short-channel effects and include two gate conductors that surround a non-planarized channel. To produce the desired finFET structure, a substrate is subjected to a manufacturing process that includes a complex series of steps, such as deposition, etching, and planarization steps, that provide suitable conductor, semiconductor, and insulating layers and form the appropriate components of the finFET structures therefrom.
Although finFETs are relatively effective when implemented into microdevices, they may be relatively costly and time-consuming to produce. As a result, manufacturers have begun exploring the use of other types of double gate devices, such as, for example, planar double gate devices. Planar double gate devices typically include a top gate, a bottom gate, and a channel interposed therebetween. Similar to finFETs, a complex series of manufacturing processes is used to produce planar double gate devices. These manufacturing processes, however, have presented certain drawbacks. For example, in some processes, the top and bottom gates may not be appropriately aligned to one another. In other instances, the gates may be of varying widths. In either case, device yield and performance may be significantly constrained, extra gate to source/drain overlap capacitance may occur, and/or loss of current drive may result.
Accordingly, it is desirable to have a high-performance semiconductor device that has appropriately aligned gate conductors that have uniform lengths. Additionally, it is desirable to have a method for manufacturing the semiconductor device that is relatively inexpensive and simple to manufacture. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.